A horizontal synchronization signal received by a monitor has a frequency usually ranging from 15 to 150 KHz. Generating a drive signal that is resynchronized with the monitor and phase-shifted by a precise value with respect to the external synchronization signal, can be a problem. When the device is balanced, the phase shift comprises a fixed value that does not vary from line to line and a dynamic value which may change from line to line. This dynamic value corresponds especially to variations in balance or fringe effects and depends on the characteristics of the monitor. This phase shift is usually processed by an analog device and thus does not make it possible to externally program these values, with the circuits of the monitor, to modify the phase-shift curves. Usually, it is sought to adjust these phase-shift curves as a function of the monitor requirements.
FIG. 1 shows a conventional phase-locked loop including a phase comparator 1, between the external synchronization signal HSYNC and the reference signal PHI1, which delivers a signed error E at its output. In this example, this error E is applied to a digital filter integrator 2 which, in an output register, provides digital information element C comprising an integer part and a fractional part. A digital filter 2 integrator of this kind is described, for example, in patent application EP A 644 654 entitled "First Order Digital Integrator and Filter" which is incorporated by reference herein and may be referred to for a detailed operation of this circuit.
This signal C is applied to a frequency synthesizer 3 that provides a synthesized signal CKGEN at output. This synthesizer makes it possible to carry out the division, by the integer value INT(C) or by the immediately greater integer value INT(C)+1, of the N phases Fi0 and Fi15 of a high frequency signal F applied to the synthesizer. This is carried out according to a principle described in the European patent application EP 0 641 083 entitled "Frequency Synthesizer" which is also incorporated by reference herein and may be referred to for a detailed operation of this circuit.
The synthesizer comprises a multiplexer MUX for the generation of the synthesized signal CKGEN. This multiplexer receives N phase signals NF0 to NF15, and outputs the synthesized signal CKGEN. The synthesizer selects the phase, among the N phases Fi0 to Fi15 of the high frequency signal F, at which the locking is achieved. This phase selection information PHISELECT controls the multiplexer MUX. In practice, the locking phase may change at each line and therefore the output signal CKGEN has phase leaps. These phase leaps cannot be greater than the difference between two consecutive phases, in the example 325 ps.
This synthesized signal CKGEN is looped to a multiplier 4, which multiplies the signal by M, to provide the resynchronized reference signal PHI1 having the same frequency as HSYNC. In the example, it is desired to have the synthesized signal CKGEN at the frequency of 24 MHZ. Starting with a high frequency signal at 192 MHZ, the digital information C is close to 8 (for 8.times.24 MHZ=192 MHZ). M is then deduced therefrom to find the frequency of the external synchronization signal HSYNC, such that the frequency of the synthesized signal CKGEN is equal to M times the frequency of HSYNC. The output of the multiplier provides the resynchronized signal PHI1 which, like CKGEN, may have phase leaps. For each line, the corresponding current locking phase is the same as that of the signal CKGEN. It is therefore the one defined by the information PHISELECT.